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LTC3730 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller
FEATURES
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DESCRIPTIO
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3-Phase Current Mode Controller with Onboard MOSFET Drivers 5% Output Current Match Optimizes Thermal Performance and Size of Inductors and MOSFETs Operational Amplifier Accomodates Mode Switching 1% VREF Accuracy Over Temperature Reduced Input and Output Capacitance Reduced Power Supply Induced Noise VOUT Programmable from 0.6V to 1.75V (IMVP III) 10% Power Good Output Indicator 250kHz to 600kHz Per Phase, PLL, Fixed Frequency PWM, Stage SheddingTM or Burst Mode(R) Operation OPTI-LOOP(R) Compensation Minimizes COUT Adjustable Soft-Start Current Ramping 4V, VIN, Undervoltage RUN/SS Reset/Reattempt Circuit Short-Circuit Shutdown Timer with Defeat Option Overvoltage Soft Latch Small 36-Lead Narrow (0.209") SSOP Package
The LTC(R)3730 is a PolyPhase(R) synchronous step-down switching regulator controller that drives all N-channel external power MOSFET stages in a phase-lockable fixed frequency architecture. The 3-phase controller drives its output stages with 120 phase separation at frequencies of up to 600kHz per phase to minimize the RMS losses in both the input and output filter capacitors. The 3-phase technique effectively triples the fundamental frequency, improving transient response while operating each controller at an optimal frequency for efficiency and ease of thermal design. Light load efficiency is optimized by using a choice of output Stage Shedding or Burst Mode technology. An internal operational amplifier provides mode selectable output voltage programming in conjunction with the internal VID voltage control DAC. Soft-start and a defeatable, timed short-circuit shutdown protect the MOSFETs and the load. Current foldback provides protection for the external MOSFETs under short-circuit or overload conditions.
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode, OPTI-LOOP and PolyPhase are registered trademarks of Linear Technology Corporation. Stage Shedding is a trademark of Linear Technology Corporation.
APPLICATIO S
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Tablet Computers High Performance Notebook Computers High Output Current DC/DC Power Supplies
TYPICAL APPLICATIO
VCC 4.5V TO 7V
VCC 10F LTC3730 BOOST1 BOOST2 BOOST3 0.1F SW3 SW2 SW1
TG1 SW1 BG1 SENSE1+ SENSE1- TG2 SW2 BG2 PGND SENSE2+ SENSE2- TG3 SW3 BG3 SENSE3+ SENSE3- VIN VIN
1H
0.003
POWER GOOD INDICATOR OPTIONAL SYNC IN
PGOOD PLLIN PLLFLTR
1H
0.003
5 VID BITS 680pF
VID0-VID4
ITH 5k 0.1F 100pF RUN/SS SGND EAIN AMPOUT IN - IN +
1H
0.003
Figure 1. High Current Triple Phase Step-Down Converter
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VIN 5V TO 28V 22F 35V VOUT 1.2V 50A
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+
COUT 470F 4V
3730 F01
1
LTC3730
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW VID1 PLLIN PLLFLTR FCB IN+ IN- AMPOUT EAIN SGND 1 2 3 4 5 6 7 8 9 36 VID0 35 PGOOD 34 BOOST1 33 TG1 32 SW1 31 BOOST2 30 TG2 29 SW2 28 VCC 27 BG1 26 PGND 25 BG2 24 BG3 23 SW3 22 TG3 21 BOOST3 20 VID4 19 VID3
Topside Driver Voltage (BOOSTN) Range .. 38V to -0.3V Switch Voltage (SWN) Range ........................ 32V to -5V Boosted Driver Voltage (BOOSTN - SWN) .... 7V to -0.3V Peak Output Current <1ms (TGN, BGN) ..................... 5A Supply Voltage (VCC), PGOOD Pin Voltage Range ....................................... 7V to -0.3V PLLIN, RUN/SS, PLLFLTR, FCB Voltages .. VCC to -0.3V ITH Voltage Range ..................................... 2.4V to -0.3V Operating Ambient Temperature Range ....... 0C to 70C Junction Temperature (Notes 2, 7) ....................... 125C Storage Temperature Range ..................-65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC3730CG
SENSE1+ 10 SENSE1- 11 SENSE2
+
12 13
SENSE2 -
SENSE3 - 14 SENSE3 + 15 RUN/SS 16 ITH 17 VID2 18
G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 125C, JA = 95C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VREGULATED VSENSEMAX IMATCH VLOADREG PARAMETER Regulated Voltage at IN+ Maximum Current Sense Threshold Maximum Current Threshold Match Output Voltage Load Regulation Main Control Loop
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = VRUN/SS = 5V unless otherwise noted.
CONDITIONS (Note 3); VID Code = 11111, VITH = 1.2V
q
MIN 0.596 0.594 65 62 -5
q q
TYP 0.600 0.600 75 75
MAX 0.604 0.606 85 88 5
UNITS V V mV mV % % % %/V mmho MHz V A V V
VEAIN = 0.5V, VITH Open, VSENSE1-, VSENSE2-, VSENSE3- = 0.6V, 1.8V Worst-Case Error at VSENSE(MAX) (Note 3) Measured in Servo Loop, ITH Voltage = 1.2V to 0.7V Measured in Servo Loop, ITH Voltage = 1.2V to 2V VCC = 4.5V to 7V ITH = 1.2V, Sink/Source 25A (Note 3) ITH = 1.2V, (gm * ZL, ZL = Series 1k-100k-1nF)
q
0.1 -0.1 0.03 3.6 0.58 5 3 0.60 0.2 3.2 3.8
0.5 -0.5 6.6 0.62 0.7 4.5
VREFLNREG gm gmOL VFCB IFCB VBINHIBIT UVR
Output Voltage Line Regulation Transconductance Amplifier gm Transconductance Amplifier GBW Forced Continuous Threshold FCB Bias Current Burst Inhibit Threshold Undervoltage RUN/SS Reset
q
q
VFCB = 0.65V Measured at FCB pin VCC Lowered Until the RUN/SS Pin is Pulled Low
VCC - 1.5 VCC - 0.7 VCC - 0.3
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W
LTC3730
ELECTRICAL CHARACTERISTICS
SYMBOL IQ PARAMETER Input DC Supply Current Normal Mode Shutdown Soft-Start Charge Current RUN/SS Pin ON Threshold RUN/SS Pin Arming Threshold RUN/SS Pin Latch-Off Threshold RUN/SS Discharge Current Shutdown Latch Disable Current SENSE Pins Source Current Maximum Duty Factor Top Gate Rise Time Top Gate Fall Time Bottom Gate Rise Time Bottom Gate Fall Time Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time Minimum On-Time Maximum Low Level Input Voltage Minimum High Level Input Voltage VID0 to VID4 Internal Pull-Up Current VID0 to VID4 PGOOD Voltage Output Low PGOOD Output Leakage PGOOD Trip Thesholds VAMPOUT Ramping Negative VAMPOUT Ramping Positive Power Good Fault Report Delay Nominal Frequency Lowest Frequency Highest Frequency PLLIN Input Threshold PLLIN Input Resistance Phase Detector Output Current Sinking Capability Sourcing Capability Controller 2-Controller 1 Phase Controller 3-Controller 1 Phase fPLLIN < fOSC fPLLIN > fOSC VVID = 0V (Note 6) IPGOOD = 2mA VPGOOD = 5V VAMPOUT with Respect to Set Output Voltage, VID Code = 11111, PGOOD Goes Low After VUVDLY Delay After VEAIN is Forced Outside VUV Threshold VPLLFLTR = 1.2V VPLLFLTR = 0V VPLLFLTR = 2.4V 360 190 600 -7 7 -10 11 100 400 225 680 1 50 20 20 120 240
q
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = VRUN/SS = 5V unless otherwise noted.
CONDITIONS (Note 4) VCC = 5V VRUN/SS = 0V, VID0 to VID4 Open VRUN/SS = 1.9V VRUN/SS, Ramping Positive VRUN/SS, Ramping Positive Until Short-Circuit Latch-Off is Armed VRUN/SS, Ramping Negative Soft-Short Condition VEAIN = 0.375V, VRUN/SS = 4.5V VEAIN = 0.375V, VRUN/SS = 4.5V SENSE1+, SENSE1-, SENSE2+, SENSE2-, SENSE3+, SENSE3- All Equal 1.2V; Current at Each Pin In Dropout, VSENSEMAX 30mV CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF All Controllers, CLOAD = 3300pF Each Driver All Controllers, CLOAD = 3300pF Each Driver Tested with a Square Wave (Note 5) 95 -5 -0.8 1 MIN TYP 2.3 20 -1.5 1.5 3.8 3.2 -1.5 1.5 13 98.5 30 40 30 20 50 60 110 0.4 2 3 - 0.25 0.1 0.25 0.3 1 -13 13 150 440 260 750 90 90 90 90 5 20 MAX 3.5 50 -2.5 1.9 4.5 UNITS mA A A V V V A A A % ns ns ns ns ns ns ns V V A % V A % % s kHz kHz kHz V k A A Deg Deg
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IRUN/SS VRUN/SS VRUN/SSARM VRUN/SSLO ISCL ISDLHO ISENSE DFMAX TG tR,tF BG tR, tF TG/BG t1D BG/TG t2D tON(MIN) VIDIL VIDIH VIDPULLUP ATTENERR VPGL IPGOOD VPGTHNEG VPGTHPOS VUVDLY fNOM fLOW fHIGH RPLLTH RPLL IN IPLL LPF
VID Parameters
Power Good Output Indication
Oscillator and Phase-Locked Loop
RRELPHS
3
LTC3730
ELECTRICAL CHARACTERISTICS
SYMBOL IB VOS CM CMRR ICL AVOL GBP SR VO(MAX) TSHDN PARAMETER Input Bias Current Input Offset Voltage Magnitude Common Mode Input Voltage Range Common Mode Rejection Ratio Output Source Current Open-Loop DC Gain Gain Bandwidth Product Slew Rate Maximum High Output Voltage Temperature Shutdown IOUT = 1mA IOUT = 1mA RL = 2k IOUT = 1mA Temperature Rising IOUT = 1mA IN+ = IN- = 1.2V, I
OUT = 1mA
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = VRUN/SS = 5V unless otherwise noted.
CONDITIONS MIN TYP 15 0.8 0 46 10 70 35 30 2 5 VCC - 1.2 VCC - 0.9 130 165 MAX 200 5 VCC - 1.4 UNITS nA mV V dB mA V/V MHz V/s V C Operational Amplifier
Overtemperature Shutdown
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. A maximum current of 200A is allowed to pull up the RUN/SS pin to prevent overcurrent shutdown. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3730CG: TJ = TA + (PD x 95C/W) Note 3: The IC is tested in a feedback loop that includes the operational amplifier in a unity-gain configuration loaded with 100A to ground driving the VID DAC into the error amplifier and servoing the resultant voltage to the midrange point for the error amplifier (VITH = 1.2V).
Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 5: The minimum on-time condition corresponds to an inductor peakto-peak ripple current of 40% of IMAX (see minimum on-time considerations in the Applications Information Section). Note 6: The ATTENERR specification is in addition to the output voltage accuracy specified at VID Code = 11111. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
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LTC3730 TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs IOUT (Figure 14)
100 90 VFCB = OPEN 80 VFCB = 5V VFCB = 0V 70 60 50 40 30 20 10 0 0.1 1 10 VIN = 8V VOUT = 1.5V 100
3730 G01
EFFICIENCY (%)
EFFICIENCY (%)
80 75 70 65 60 55 50 0 5
IOUT = 45A
EFFICIENCY (%)
INDUCTOR CURRENT (A)
Reference Voltage vs Temperature
610 6.0
605
MAXIMUM ISENSE THRESHOLD (mV)
ERROR AMPLIFIER gm (mmho)
REFERENCE VOLTAGE (mV)
600
595
590 -50 -30 -10
10 30 50 70 TEMPERATURE (C)
Oscillator Frequency vs Temperature
700
OSCILLATOR FREQUENCY (kHz)
600 500 400
VPLLFLTR = 2.4V
UNDER VOLTAGE RESET (V)
VPLLFLTR = 5V
FREQUENCY (kHz)
VPLLFLTR = 1.2V 300 200 100 0 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90 VPLLFLTR = 0V
UW
90
3730 G04 3730 G07
Efficiency vs VIN (Figure 14)
100 95 90 85 IOUT = 15A VOUT = 1.5V f = 250kHz 100
Efficiency vs Frequency (Figure 14)
ILOAD = 20A VOUT = 1.5V 95 VIN = 5V 90 VIN = 12V 85 VIN = 20V 80 VIN = 8V
10
15 VIN (V)
20
25
3730 G02
75 200
300
400 FREQUENCY (kHz)
500
600
3730 G03
Error Amplifier gm vs Temperature
85
Maximum ISENSE Threshold vs Temperature
5.5
80 VO = 1.75V 75 VO = 0.6V 70
5.0
4.5
110
4.0 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
75
90
65 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
75
90
3730 G05
3730 G06
Oscillator Frequency vs VPLLFLTR
700 5
Undervoltage Reset Voltage vs Temperature
600
4
500
3
400
2
300
1
200 0 0.5 1 1.5 2 PLLFLTR PIN VOLTAGE (V) 2.5
3730 G08
0 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
75
90
3730 G09
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5
LTC3730 TYPICAL PERFOR A CE CHARACTERISTICS
Short-Circuit Arming and Latchoff vs Temperature
5 2.8 ARMING
RUN/SS PIN VOLTAGE (V)
4
SUPPLY CURRENT (mA)
2.4 LATCHOFF 2.0 1.6 1.2 0.8
80
RUN/SS PULLUP CURRENT (A)
3
2
1 0.4 0 -45 -30 -15 0 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
Maximum ISENSE vs VRUN/SS
80 70
MAXIMUM ISENSE (mV) ISENSE VOLTAGE (mV)
ISENSE VOLTAGE THRESHOLD (mV)
60 50 40 30 20 10 0 0 1 3 4 VRUN/SS VOLTAGE (V) 2 5 6
3730 G13
Percentage of Nominal Output vs Peak ISENSE (Foldback)
80 70
MAXIMUM DUTY FACTOR (%) PEAK ISENSE VOLTAGE (mV)
60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 PERCENTAGE OF NOMINAL OUTPUT VOLTAGE (%)
3730 G15
ISENSE PIN CURRENT (A)
6
UW
75
3730 G10
Supply Current vs Temperature
100 VCC = 5V
SHUTDOWN CURRENT (A)
RUN/SS Pull-Up Current vs Temperature
2.5 VRUN/SS = 1.9V
2.0
60
1.5
40
1.0
20
0.5
0 0 15 30 45 60 TEMPERATURE (C) 75 90
90
0 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
75
90
3730 G11
3730 G12
Maximum Current Sense Threshold vs Duty Factor
75 75 60 45 30 15 0 -15
Peak Current Threshold vs VITH
50
25
0 0 20 40 60 DUTY FACTOR (%) 80 100
3730 G13a
0
0.6
1.2 VITH (V)
1.8
2.4
3730 G14
Maximum Duty Factor vs Temperature
100 VPLLFLTR = 0V 98 30 20 10 0 -10 -20 90 -45 -30 -15 -30 40
ISENSE Pin Current vs VOUT
96
94
92
0 15 30 45 60 TEMPERATURE (C)
75
90
0
1
3 2 VOUT (V)
4
5
3730 G17
3730 G16
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LTC3730 TYPICAL PERFOR A CE CHARACTERISTICS
Operational Amplifier Gain-Phase
60 50
GAIN (dB)
IN 1k
100F 100k 0.1 1
Shed Mode at 1Amp, Light Load Current (Circuit of Figure 14)
VOUT AC, 20mV/DIV
VSW1 10V/DIV VSW2 10V/DIV VSW3 10V/DIV 4s/DIV VIN = 12V VOUT = 1.5V VFCB = VCC FREQUENCY = 250kHz
3730 G20
Continuous Mode at 1Amp, Light Load Current (Circuit of Figure 14)
VOUT AC, 20mV/DIV
VSW1 10V/DIV VSW2 10V/DIV VSW3 10V/DIV VIN = 12V 4s/DIV VOUT = 1.5V VFCB = 0V FREQUENCY = 250kHz ILOAD 20A/DIV
3730 G22
+
-
UW
40 30 20 10 0 0 -30 -60 -90 -120 5k -150 1000
3730 G19
PHASE (DEG)
10 100 FREQUENCY (kHz)
Burst Mode at 1Amp, Light Load Current (Circuit of Figure 14)
VOUT AC, 20mV/DIV
VSW1 10V/DIV VSW2 10V/DIV VSW3 10V/DIV 4s/DIV VIN = 12V VOUT = 1.5V VFCB = OPEN FREQUENCY = 250kHz
3730 G21
Transient Load Current Response: 0Amp to 50Amp (Circuit of Figure 14)
VOUT AC, 20mV/DIV
VIN = 12V 20s/DIV VOUT = 1.5V VFCB = VCC FREQUENCY = 250kHz
3730 G23
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LTC3730
PI FU CTIO S
VID0 to VID4 (Pins 1, 18, 19, 20, 36): Output Voltage Programming Input Pins. A 3A internal pull-up current is provided on each input pin. See Table 1 for details. Do not apply voltage to these pins prior to the application of voltage on the VCC pin. PLLIN (Pin 2): Synchronization Input to Phase Detector. This pin is internally terminated to SGND with 50k. The phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the PLLIN signal. PLLFLTR (Pin 3): The phase-locked loop's lowpass filter is tied to this pin. Alternatively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator. (Do not apply voltage to this pin prior to the application of voltage on the VCC pin.) FCB (Pin 4): Forced Continuous Control Input. The voltage applied to this pin sets the operating mode of the controller. The forced continuous current mode is active when the applied voltage is less than 0.6V. Burst Mode operation will be active when the pin is allowed to float and a stage shedding mode will be active if the pin is tied to the VCC pin. (Do not apply voltage to this pin prior to the application of voltage on the VCC pin.) IN+, IN- (Pins 5, 6): Inputs to an Operational Amplifier. AMPOUT (Pin 7): Output of the Operational Amplifier. This amplifier can be used as a switchable voltage gain amplifier to determine the output voltage or as a remote sensing amplifier. EAIN (Pin 8): This is the input to the error amplifier which compares the internally VID divided output voltage to the internal 0.6V reference voltage. SGND (Pin 9): Signal Ground. This pin must be routed separately under the IC to the PGND pin and then to the main ground plane. SENSE1+, SENSE2+, SENSE3+, SENSE1-, SENSE2-, SENSE3- (Pins 10 to 15): The Inputs to Each Differential Current Comparator. The ITH pin voltage and built-in offsets between SENSE- and SENSE+ pins, in conjunction with RSENSE, set the current trip threshold level. RUN/SS (Pin 16): Combination of Soft-Start, Run Control Input and Short-Circuit Detection Timer. A capacitor to ground at this pin sets the ramp time to full current output as well as the time delay prior to an output voltage short-circuit shutdown. A minimum value of 0.01F is recommended on this pin. ITH (Pin 17): Error Amplifier Output and Switching Regulator Compensation Point. All three current comparator's thresholds increase with this control voltage. PGND (Pin 26): Driver Power Ground. This pin connects to the sources of the bottom N-channel external MOSFETs and the (-) terminals of CIN. BG1 to BG3 (Pins 27, 25, 24): High Current Gate Drives for Bottom N-Channel MOSFETs. Voltage swing at these pins is from ground to VCC. VCC (Pin 28): Main Supply Pin. Because this pin supplies both the controller circuit power as well as the high power pulses supplied to drive the external MOSFET gates, this pin needs to be very carefully and closely decoupled to the IC's PGND pin. SW1 to SW3 (Pins 32, 29, 23): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN (where VIN is the external MOSFET supply rail). TG1 to TG3 (Pins 33, 30, 22): High Current Gate Drives for Top N-channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to the boost voltage source superimposed on the switch node voltage SW. BOOST1 to BOOST3 (Pins 34, 31, 21): Positive Supply Pins to the Topside Floating Drivers. Bootstrapped capacitors, charged with external Schottky diodes and a boost voltage source, are connected between the BOOST and SW pins. Voltage swing at the BOOST pins is from boost source voltage (typically VCC) to this boost source voltage +VIN (where VIN is the external MOSFET supply rail). PGOOD (Pin 35): This open-drain output is pulled low when the output voltage has been outside the PGOOD tolerance window for the VUVDLY delay of approximately 100s.
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LTC3730
FU CTIO AL DIAGRA
PLLIN FIN 50k RLP PLLFLTR CLP OSCILLATOR PHASE DET
FCB FCB - 100s DELAY PROTECTION IN+ + EAIN - + 0.54V B 0.55V - A1 + I1 R1 20k EAIN 0.600V VFB - + + 0.660V ITH CC R2 VARIABLE RC 5-BIT VID DECODER 6V 1.5A VCC
SHDN RST
0.6V PGOOD**
IN -
AMPOUT
EA OV
SS CLAMP
54k 2.4V
54k
VOUT
- SHED 0.600V RUN SOFTSTART INTERNAL SUPPLY SGND UV RESET RUN/SS VREF VCC VCC
5(VFB)
+
CCC
VID0 VID1 VID2 VID3 VID4 CSS
3730 F02
Figure 2
OPERATIO
(Refer to Functional Diagram)
Main Control Loop The IC uses a constant frequency, current mode stepdown architecture. During normal operation, each top MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the main current comparator, I1, resets each RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The EAIN pin receives a portion of this voltage feedback signal via the AMPOUT pin through the
internal VID DAC and is compared to the internal reference voltage. When the load current increases, it causes a slight decrease in the EAIN pin voltage relative to the 0.6V reference, which in turn causes the ITH voltage to increase until each inductor's average current matches one third of the new load current (assuming all three current sensing resistors are equal). In Burst Mode operation and stage shedding mode, after each top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle.
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CLK1 CLK2 CLK3 DUPLICATE FOR SECOND AND THIRD CONTROLLER CHANNELS BOOST DROP OUT DET 0.66V RS LATCH S R Q Q VCC DB VIN BOT FORCE BOT SWITCH LOGIC VCC FCB SHDN - + - + L BOT BG PGND SW TOP TG CB
-
+
U
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CIN
-
++
3mV
-
I2
VCC
+ 36k SENSE
SLOPE COMP 5(VFB) 0.86V
- 36k SENSE
RSENSE
COUT
9
LTC3730
OPERATIO
The top MOSFET drivers are biased from floating bootstrap capacitor CB, which is normally recharged during each off cycle, through an external Schottky diode. When VIN decreases to a voltage close to VOUT, however, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector counts the number of oscillator cycles that the bottom MOSFET remains off and periodically forces a brief on period to allow CB to recharge. The main control loop is shut down by pulling the RUN/SS pin low. Releasing RUN/SS allows an internal 1.5A current source to charge soft-start capacitor CSS. When CSS reaches 1.5V, the main control loop is enabled and the internally buffered ITH voltage is clamped but allowed to ramp as the voltage on CSS continues to ramp. This "softstart" clamping prevents abrupt current from being drawn from the input power source. When the RUN/SS pin is low, all functions are kept in a controlled state. The RUN/SS pin is pulled low when the VCC input voltage is below 4V or when the IC die temperature rises above 150C. Low Current Operation The FCB pin is a multifunction pin: 1) an analog comparator input to provide regulation for a secondary winding by forcing temporary forced PWM operation and 2) a logic input to select between three modes of operation. A) Burst Mode Operation When the FCB pin voltage is below 0.6V, the controller performs as a continuous, PWM current mode synchronous switching regulator. The top and bottom MOSFETs are alternately turned on to maintain the output voltage independent of direction of inductor current. When the FCB pin is below VCC - 1.5V but greater than 0.6V, the controller performs as a Burst Mode switching regulator. Burst Mode operation sets a minimum output current level before turning off the top switch and turns off the synchronous MOSFET(s) when the inductor current goes negative. This combination of requirements will, at low current, force the ITH pin below a voltage threshold that will temporarily shut off both output MOSFETs until the output voltage drops slightly. There is a burst comparator having 60mV of hysteresis tied to the ITH pin. This hysteresis
10
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(Refer to Functional Diagram)
results in output signals to the MOSFETs that turn them on for several cycles, followed by a variable "sleep" interval depending upon the load current. The resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. B) Stage Shedding Operation When the FCB pin is tied to the VCC pin, Burst Mode operation is disabled and the forced minimum inductor current requirement is removed. This provides constant frequency, discontinuous current operation over the widest possible output current range. At approximately 10% of maximum designed load current, the second and third output stages are shut off and the first output stage alone is active in discontinuous current mode. This "stage shedding" optimizes efficiency by eliminating the gate charging losses and switching losses of the other two output stages. Additional cycles will be skipped when the output load current drops below 1% of maximum designed load current in order to maintain the output voltage. This Stage Shedding operation is not as efficient as Burst Mode operation at very light loads, but does provide lower noise, constant frequency operating mode down to light load conditions. C) Continuous Current Operation Tying the FCB pin to ground will force continuous current operation. This is the least efficient operating mode, but may be desirable in certain applications. The output can source or sink current in this mode. When forcing continuous operation and sinking current, this current will be forced back into the main power supply, potentially boosting the input supply to dangerous voltage levels-- BEWARE! Frequency Synchronization The phase-locked loop allows the internal oscillator to be synchronized to an external source using the PLLIN pin. The output of the phase detector at the PLLFLTR pin is also the DC frequency control input of the oscillator which operates over a 250kHz to 600kHz range corresponding to a voltage input from 0V to 2.4V. When locked, the PLL aligns the turn on of the top MOSFET to the rising edge of
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LTC3730
OPERATIO
the synchronizing signal. When no frequency information is supplied to the PLLIN pin, PLLFLTR goes low, forcing the oscillator to minimum frequency. A DC source can be applied to the PLLFLTR pin to externally set the desired operating frequency. An approximate 20A discharge current will be present at the pin with no PLLIN signal. Input capacitance ESR requirements and efficiency losses are reduced substantially in a multiphase architecture because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the RMS current squared. A 3-stage, single output voltage implementation can reduce input path power loss by 90%. Operational Amplifier This amplifier can be used to satisfy output voltage requirements that change according to the mode of circuit or CPU operation. The output voltage can be dropped several hundred millivolts when using an externally switched resistive divider based upon the activity level or speed requirement by changing the output voltage feedback factor. The amplifier can swing to within 1.2V of the positive power supply at low output current (1mA). The amplifier has an output slew rate of 5V/s and is capable of driving capacitive loads at an output sourcing RMS current of up to 10mA. Power Good The PGOOD pin is connected to the drain of an internal N-channel MOSFET. The MOSFET is turned on once an internal delay has elapsed and the output voltage has been away from its nominal value by greater than 10%. If the output returns to normal prior to the delay timeout, the timer is reset. There is no delay time for the rising of the PGOOD output once the output voltage is within the 10% "window."
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(Refer to Functional Diagram)
Short-Circuit Detection The RUN/SS capacitor is used initially to turn on and limit the inrush current from the input power source. Once the controllers have been given time, as determined by the capacitor on the RUN/SS pin, to charge up the output capacitors and provide full load current, the RUN/SS capacitor is then used as a short-circuit timeout circuit. If the output voltage falls to less than 70% of its nominal output voltage, the RUN/SS capacitor begins discharging, assuming that the output is in a severe overcurrent and/or short-circuit condition. If the condition lasts for a long enough period, as determined by the size of the RUN/SS capacitor, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overridden by providing >5A at a compliance of 3.8V to the RUN/SS pin. This additional current shortens the softstart period but prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. Foldback current limit can be overridden by clamping the EAIN pin such that the voltage is held above the (70%)(0.6V) or 0.42V level even when the actual output voltage is low. Input Undervoltage Reset The RUN/SS capacitor will be reset if the input voltage, (VCC) is allowed to fall below approximately 3.8V. The capacitor on the pin will be discharged until the shortcircuit arming latch is disarmed. The RUN/SS capacitor will attempt to cycle through a normal soft-start ramp up after the VCC supply rises above 3.8V. This circuit prevents power supply latchoff in the event of input power switching break-before-make situations. The PGOOD pin is held low during start-up until the RUN/SS capacitor rises above the short-circuit latchoff arming threshold of approximately 3.8V.
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The basic application circuit is shown in Figure 1 on the first page of this data sheet. External component selection is driven by the load requirement, and normally begins with the selection of an inductance value based upon the desired operating frequency, inductor current and output voltage ripple requirements. Once the inductors and operating frequency have been chosen, the current sensing resistors can be calculated. Next, the power MOSFETs and Schottky diodes are selected. Finally, C IN and COUT are selected according to the required voltage ripple requirements. The circuit shown in Figure 1 can be configured for operation up to a MOSFET supply voltage of 28V (limited by the external MOSFETs and possibly the minimum on-time). Operating Frequency The IC uses a constant frequency, phase-lockable architecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the PLLFLTR pin. Refer to the Phase-Locked Loop and Frequency Synchronization section for additional information. A graph for the voltage applied to the PLLFLTR pin versus frequency is given in Figure 3. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 720kHz.
700 OSCILLATOR FREQUENCY (kHz)
600
500
400
300
200 0 0.5 1 1.5 2 PLLFLTR PIN VOLTAGE (V) 2.5
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Figure 3. Oscillator Frequency vs VPLLFLTR
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Inductor Value Calculation and Output Ripple Current The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge and transition losses. In addition to this basic tradeoff, the effect of inductor value on ripple current and low current operation must also be considered. The PolyPhase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency. The inductor value has a direct effect on ripple current. The inductor ripple current IL per individual section, N, decreases with higher inductance or frequency and increases with higher VIN or VOUT:
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IL =
VOUT VOUT 1- fL VIN
where f is the individual output stage operating frequency. In a PolyPhase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to the ripple cancellation. The details on how to calculate the net output ripple current can be found in Application Note 77. Figure 4 shows the net ripple current seen by the output capacitors for the different phase configurations. The output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. The output ripple current is normalized against the inductor ripple current at zero duty factor. The graph can be used in place of tedious calculations. As shown in Figure 4, the zero output ripple current is obtained when:
VOUT k where k = 1, 2, ..., N - 1 = VIN N
So the number of phases used can be selected to minimize the output ripple current and therefore the output ripple voltage at the given input and output voltages. In applications having a highly varying input voltage, additional phases will produce the best results.
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Accepting larger values of IL allows the use of low inductances but can result in higher output voltage ripple. A reasonable starting point for setting ripple current is IL = 0.4(IOUT)/N, where N is the number of channels and IOUT is the total load current. Remember, the maximum IL occurs at the maximum input voltage. The individual inductor ripple currents are constant determined by the inductor, input and output voltages.
1.0 0.9 0.8 0.7 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE
IO(P-P) VO/fL
0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9
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Figure 4. Normalized Peak Output Current vs Duty Factor [IRMS = 0.3(IO(P-P))]
Inductor Core Selection Once the value for L1 to L3 is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of ferrite, molypermalloy or Kool M(R) cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than
Kool M is a registered trademark of Magnetics, Inc.
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ferrite. A reasonable compromise from the same manufacturer is Kool M. Toroids are very space efficient, especially when you can use several layers of wire. Because they lack a bobbin, mounting is more difficult. However, designs for surface mount are available which do not increase the height significantly. Power MOSFET and D1, D2, D3 Selection At least two external power MOSFETs must be selected for each of the three output sections: One N-channel MOSFET for the top (main) switch and one or more N-channel MOSFET(s) for the bottom (synchronous) switch. The number, type and "on" resistance of all MOSFETs selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the MOSFET will be used. A much smaller and much lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output voltage that is less than 1/3 of the input voltage. In applications where VIN >> VOUT, the top MOSFETs' "on" resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide reasonably low "on" resistance with significantly reduced input capacitance for the main switch application in switching regulators. The peak-to-peak MOSFET gate drive levels are set by the voltage, VCC, requiring the use of logic-level threshold MOSFETs in most applications. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the "on" resistance RDS(ON), input capacitance, input voltage and maximum output current. MOSFET input capacitance is a combination of several components but can be taken from the typical "gate charge" curve included on most data sheets. The curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. The initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. The flat portion of the curve is the result of the Miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. The upper sloping line is due to the
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drain-to-gate accumulation capacitance and the gate-tosource capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given VDS drain voltage, but can be adjusted for different VDS voltages by multiplying by the ratio of the application VDS to the curve specified VDS values. A way to estimate the CMILLER term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. CRSS and COS are specified sometimes but definitions of these parameters are not included.
VIN MILLER EFFECT VGS a QIN CMILLER = (QB - QA)/VDS b V
+
VGS
+V DS -
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-
Figure 5
When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN
V -V Synchronous Switch Duty Cycle = IN OUT VIN The power dissipation for the main and synchronous MOSFETs at maximum output current are given by: I V PMAIN = OUT MAX 1 + RDS(ON) + VIN N
2
()
VIN
(RDR )(C MILLER ) * 2N 1 1 + ( f ) VCC - VTH(IL) VTH(IL)
2 IMAX
PSYNC =
VIN - VOUT IMAX 1 + RDS(ON) VIN N
2
()
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where N is the number of output stages, is the temperature dependency of RDS(ON), RDR is the effective top driver resistance (approximately 2 at VGS = VMILLER), VIN is the drain potential and the change in drain potential in the particular application. VTH(IL) is the data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current. CMILLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For VIN < 12V, the high current efficiency generally improves with larger MOSFETs, while for VIN > 12V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short circuit when the synchronous switch is on close to 100% of the period. The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but = 0.005/C can be used as an approximation for low voltage MOSFETs. The Schottky diodes, D1 to D3 shown in Figure 1 conduct during the dead time between the conduction of the two large power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead time and requiring a reverse recovery period which could cost as much as several percent in efficiency. A 2A to 8A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition loss due to their larger junction capacitance. CIN and COUT Selection In continuous mode, the source current of each top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a close form equation can be found in Application Note 77. Figure 6 shows the input capacitor ripple current for different phase configu3730f
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rations with the output voltage fixed and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple current can be achieved when the product of phase number and output voltage, N(VOUT), is approximately equal to the input voltage VIN or:
VOUT k = where k = 1, 2, ..., N - 1 VIN N
So the phase number can be chosen to minimize the input capacitor size for the given input and output voltages. In the graph of Figure 4, the local maximum input RMS capacitor currents are reached when:
VOUT 2k - 1 where k = 1, 2, ..., N = VIN N
These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question. The Figure 6 graph shows that the peak RMS input current is reduced linearly, inversely proportional to the number N
0.6 0.5 0.4 0.3 0.2 0.1 0 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE
RMS INPUT RIPPLE CURRNET DC LOAD CURRENT
0.1
0.2
0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN)
0.8
0.9
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Figure 6. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Output Stages
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of stages used. It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 3-stage implementation results in 90% less power loss when compared to a single phase design. Battery/input protection fuse resistance (if used), PC board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a PolyPhase system. The required amount of input capacitance is further reduced by the factor, N, due to the effective increase in the frequency of the current pulses. Ceramic capacitors are becoming very popular for small designs but several cautions should be observed. "X7R", "X5R" and "Y5V" are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions applied. Physically, if the capacitance value changes due to applied voltage change, there is a concommitant piezo effect which results in radiating sound! A load that draws varying current at an audible rate may cause an attendant varying input voltage on a ceramic capacitor, resulting in an audible signal. A secondary issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. The voltage can increase at a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! Ceramic capacitors, when properly selected and used however, can provide the lowest overall loss due to their extremely low ESR. The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR requirement is satisfied the capacitance is adequate for filtering. The steady-state output ripple (VOUT) is determined by:
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1 VOUT IRIPPLE ESR + 8NfC OUT
where f = operating frequency of each stage, N is the number of output stages, COUT = output capacitance and IL = ripple current in each inductor. The output ripple is highest at maximum input voltage since IL increases with input voltage. The output ripple will be less than 50mV at max VIN with IL = 0.4IOUT(MAX) assuming:
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COUT required ESR < N * RSENSE and COUT > 1/(8Nf)(RSENSE)
The emergence of very low ESR capacitors in small, surface mount packages makes very small physical implementations possible. The ability to externally compensate the switching regulator loop using the ITH pin allows a much wider selection of output capacitor types. The impedance characteristics of each capacitor type is significantly different than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo and the Panasonic SP surface mount types have a good (ESR)(size) product. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. Ceramic capacitors from AVX, Taiyo Yuden, Murata and Tokin offer high capacitance value and very low ESR, especially applicable for low output voltage applications. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV, the KEMET T510 series of surface-mount tantalums or the Panasonic SP series of surface mount special polymer capacitors available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo POS-CAP, Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. RSENSE Selection for Output Current Once the frequency and inductor have been chosen, RSENSE1, RSENSE2, RSENSE3 are determined based on the required peak inductor current. The current comparator
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has a typical maximum threshold of 75mV/RSENSE and an input common mode range of SGND to (1.1) * VCC. The current comparator threshold sets the peak inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, IL. Allowing a margin for variations in the IC and external component values yields:
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RSENSE = N
50mV IMAX
The IC works well with values of RSENSE from 0.002 to 0.02. VCC Decoupling The VCC pin supplies power not only the internal circuits of the controller but also the top and bottom gate drivers on the IC and therefore must be bypassed very carefully to ground with a ceramic capacitor, type X7R or X5R (depending upon the operating temperature environment) of at least 1F immediately next to the IC and preferably an additional 10F placed very close to the IC due to the extremely high instantaneous currents involved. The total capacitance, taking into account the voltage coefficient of ceramic capacitors, should be 100 times as large as the total combined gate charge capacitance of ALL of the MOSFETs being driven. Good bypassing close to the IC is necessary to supply the high transient currents required by the MOSFET gate drivers while keeping the 5V supply quiet enough so as not to disturb the very small-signal high bandwidth of the current comparators. Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors, CB, connected to the BOOST pins, supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though diode DB from VCC when the SW pin is low. When one of the topside MOSFETs turns on, the driver places the CB voltage across the gate-source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply (VBOOST = VCC + VIN). The value of the boost capacitor CB needs to be
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30 to 100 times that of the total gate charge capacitance of the topside MOSFET(s) as specified on the manufacturer's data sheet. The reverse breakdown of DB must be greater than VIN(MAX). Operational Amplifier The amplifier has a 0 to VCC - 1.4V common mode input range and an output swing range of 0 to VCC - 1.2V. The output uses an NPN emitter follower without any internal pull-down current. A DC resistive load to ground is required in order to sink current. Output Voltage The IC includes a digitally controlled 5-bit attenuator between the AMPOUT pin and the EAIN pin resulting in output voltages as defined in Table 1. Output voltages with 25mV increments are produced from 0.6V to 1V and 50mV increments from 1V to 1.75V. Each VID digital input is pulled up to a logical high with an internal 3A. The input logic threshold is approximately 1.2V but the input circuit can withstand an input voltage of up to 7V.
Table 1. VID Output Voltage Programming
CODE B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 B2 B1 B0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0.600V 0.625V 0.650V 0.675V 0.700V 0.725V 0.750V 0.775V 0.800V 0.825V 0.850V 0.875V 0.900V 0.925V 0.950V 0.975V VOUT B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 CODE B3 B2 B1 B0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1.000V 1.050V 1.100V 1.150V 1.200V 1.250V 1.300V 1.350V 1.400V 1.450V 1.500V 1.550V 1.600V 1.650V 1.700V 1.750V VOUT
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Soft-Start/Run Function The RUN/SS pin provides three functions: 1) ON/OFF, 2) soft-start and 3) a defeatable short-circuit latch off timer. Soft-start reduces the input power sources' surge currents by gradually increasing the controller's current limit (proportional to an internal buffered and clamped VITH). The latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. A small pull-up current (>5A) supplied to the RUN/SS pin will prevent the overcurrent latch from operating. A maximum pull-up current of 200A is allowed into the RUN/SS pin even though the voltage at the pin may exceed the absolute maximum rating for the pin. This is a result of the limited current and the internal protection circuit on the pin. The following explanation describes how this function operates. An internal 1.5A current source charges up the CSS capacitor. When the voltage on RUN/SS reaches 1.5V, the controller is permitted to start operating. As the voltage on RUN/SS increases from 1.5V to 3V, the internal current limit is increased from 0V/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking an additional 1s/F to reach full current. The output current thus ramps up slowly, eliminating the starting surge current required from the input power supply. If RUN/SS has been pulled all the way to ground, there is a delay before starting of approximately: tDELAY = tIRAMP 1.5V C SS = (1s/F) C SS 1.5A 3V - 1.5V = C SS = (1s/F) C SS 1.5A By pulling the RUN/SS controller pin below 0.4V the IC is put into low current shutdown (IQ < 50A). The RUN/SS pin can be driven directly from logic as shown in Figure7. Diode, D1, in Figure 7 reduces the start delay but allows CSS to ramp up slowly providing the soft-start function. The RUN/SS pin has an internal 6V zener clamp (see the Functional Diagram).
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Fault Conditions: Overcurrent Latchoff
The RUN/SS pins also provide the ability to latch off the controllers when an overcurrent condition is detected. The RUN/SS capacitor is used initially to turn on and limit the inrush current of all three output stages. After the controllers have been started and been given adequate time to charge up the output capacitor and provide full load current, the RUN/SS capacitor is used for a short-circuit timer. If the output voltage falls to less than 70% of its nominal value, the RUN/SS capacitor begins discharging on the assumption that the output is in an overcurrent condition. If the condition lasts for a long enough period, as determined by the size of the RUN/SS capacitor, the discharge current, and the circuit trip point, the controller will be shut down until the RUN/SS pin voltage is recycled. If the overload occurs during start-up, the time can be approximated by: tLO1 >> (CSS * 0.6V)/(1.5A) = 4 * 105 (CSS) If the overload occurs after start-up, the voltage on the RUN/SS capacitor will continue charging and will provide additional time before latching off: tLO2 >> (CSS * 3V)/(1.5A) = 2 * 106 (CSS) This built-in overcurrent latchoff can be overridden by providing a pull-up resistor to the RUN/SS pin from VCC as shown in Figure 7. When VCC is 5V, a 200k resistance will prevent the discharge of the RUN/SS capacitor during an overcurrent condition but also shortens the soft-start period, so a larger RUN/SS capacitor value may be required.
VCC RUN/SS PIN 3.3V OR 5V RUN/SS PIN 5V D1 SHDN CSS SHDN CSS
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RSS
Figure 7. RUN/SS Pin Interfacing
Why should you defeat overcurrent latchoff? During the prototyping stage of a design, there may be a problem with noise pick-up or poor layout causing the protection circuit to latch off the controller. Defeating this feature allows troubleshooting of the circuit and PC layout. The internal foldback current limiting still remains active, thereby
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protecting the power supply system from failure. A decision can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor. The value of the soft-start capacitor CSS may need to be scaled with output current, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: CSS > (COUT )(VOUT) (10 -4) (RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1F will be sufficient for most applications. Current Foldback In certain applications, it may be desirable to defeat the internal current foldback function. A negative impedance is experienced when powering a switching regulator. That is, the input current is higher at a lower VIN and decreases as VIN is increased. Current foldback is designed to accommodate a normal, resistive load having increasing current draw with increasing voltage. The EAIN pin should be artificially held 70% above its nominal operating level of 0.6V, or 0.42V in order to prevent the IC from "folding back" the peak current level. A suggested circuit is shown in Figure 8.
VCC VCC LTC3730 Q1 CALCULATE FOR 0.42V TO 0.55V EAIN
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Figure 8. Foldback Current Elimination
The emitter of Q1 will hold up the EAIN pin to a voltage in the absence of VOUT that will prevent the internal sensing circuitry from reducing the peak output current. Removing the function in this manner eliminates the external MOSFET's protective feature under short-circuit conditions. This technique will also prevent the short-circuit latchoff function from turning off the part during a shortcircuit event and the peak output current will only be limited to N * 75mV/RSENSE.
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Undervoltage Reset
In the event that the input power source to the IC (VCC) drops below 3.8V, the RUN/SS capacitor will be discharged to ground. When VCC rises above 3.8V, the RUN/ SS capacitor will be allowed to recharge and initiate another soft-start turn-on attempt. This may be useful in applications that switch between two supplies that are not diode connected, but note that this cannot make up for the resultant interruption of the regulated output. Phase-Locked Loop and Frequency Synchronization The IC has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET of output stage 1's turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is 50% around the center frequency fO. A voltage applied to the PLLFLTR pin of 1.2V corresponds to a frequency of approximately 400kHz. The nominal operating frequency range of the IC is 225kHz to 680kHz. The phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector will not lock the internal oscillator to harmonics of the input frequency. The PLL hold-in range, fH, is equal to the capture range, fC: fH = fC = 0.5 fO The output of the phase detector is a complementary pair of current sources charging or discharging the external filter components on the PLLFLTR pin. A simplified block diagram is shown in Figure 9.
PHASE DETECTOR/ OSCILLATOR EXTERNAL OSC OSC PLLFLTR PLLIN DIGITAL PHASE/ FREQUENCY DETECTOR 2.4V RLP 10k CLP
50k
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Figure 9. Phase-Locked Loop Block Diagram
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If the external frequency (fPLLIN) is greater than the oscillator frequency, fOSC, current is sourced continuously, pulling up the PLLFLTR pin. When the external frequency is less than fOSC, current is sunk continuously, pulling down the PLLFLTR pin. If the external and internal frequencies are the same, but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus, the voltage on the PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point, the phase comparator output is open and the filter capacitor CLP holds the voltage. The IC PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. When using multiple ICs for a phase-locked system, the PLLFLTR pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the master's frequency. A voltage of 1.7V or below applied to the master oscillator's PLLFLTR pin is recommended in order to meet this requirement. The resultant operating frequency will be approximately 550kHz for 1.7V. The loop filter components (CLP, RLP) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP =10k and CLP ranges from 0.01F to 0.1F. Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest time duration that the IC is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge of the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that:
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tON(MIN) <
VOUT VIN ( f)
If the duty cycle falls below what can be accommodated by the minimum on-time, the IC will begin to skip every other cycle, resulting in half-frequency operation. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase.
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The minimum on-time for the IC is generally about 110ns. However, as the peak sense voltage decreases the minimum on-time gradually increases. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. If an application can operate close to the minimum ontime limit, an inductor must be chosen that is low enough in value to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule, keep the inductor ripple current for each channel equal to or greater than 30% of IOUT(MAX) at VIN(MAX). Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ILOAD * ESR, where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT, generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior, but also provides a DC coupled and AC filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly
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second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.2 to 5 times their suggested values) to maximize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 80% of full load current having a rise time of <2s will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step, resulting from the step change in output current, may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If CLOAD is greater than 2% of COUT , the switch rise time should be controlled so that the load rise time is limited to approximately 1000 * RSENSE * CLOAD. Thus a 250F capacitor and a 2m RSENSE resistor would require a 500s rise time, limiting the charging current to about 1A.
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LTC3730
APPLICATIO S I FOR ATIO
Automotive Considerations: Plugging into the Cigarette Lighter As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main battery line in an automobile is the source of a number of nasty potential transients, including load dump, reverse battery and double battery. Load dump is the result of a loose battery cable. When the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60V which takes several hundred milliseconds to decay. Reverse battery is just what it says, while double battery is a consequence of tow-truck operators finding that a 24V jump start cranks cold engines faster than 12V. The network shown in Figure 10 is the most straightforward approach to protect a DC/DC converter from the ravages of an automotive battery line. The series diode prevents current from flowing during reverse battery, while the transient suppressor clamps the input voltage during load dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. Although the IC has a maximum input voltage of 32V on the SW pins, most applications will be limited to 30V by the MOSFET BVDSS.
VBAT 12V VCC 5V
+
LTC3730
3730 F10
Figure 10. Automotive Application Protection
Design Example (Using Three Phases) As a design example, assume VCC = 5V, VIN = 12V(nominal), VIN = 20V(max), VOUT = 1.3V, IMAX = 45A and f = 400kHz. The inductance value is chosen first based upon a 30% ripple current assumption. The highest value of ripple current in each output stage occurs at the maximum input
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voltage. Apply a 400kHz signal into the PLLIN pin or apply 1.2V to the PLLFLTR pin.
L= = VOUT VOUT 1- VIN f I 0.68H
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(
1.3V 1- 20V 400kHz 30% 15A 1.3V
()
)( )( )
Using L = 0.6H, a commonly available value results in 34% ripple current. The worst-case output ripple for the three stages operating in parallel will be less than 11% of the peak output current. RSENSE1, RSENSE2 and RSENSE3 can be calculated by using a conservative maximum sense current threshold of 65mV and taking into account half of the ripple current:
RSENSE =
65mV = 0.0037 34% 15A 1 + 2
Use a commonly available 0.003 sense resistor. Next verify the minimum on-time is not violated. The minimum on-time occurs at maximum VCC:
tON(MIN) =
VIN(MAX) ( f)
VOUT
=
1.3V = 162ns 20V(400kHz )
The output voltage will be set by the VID code according to Table 1. The power dissipation on the topside MOSFET can be estimated. Using a Fairchild FDS6688 for example, RDS(ON) = 7m, CMILLER = 15nC/15V = 1000pF. At maximum input voltage with T(estimated) = 50C: PMAIN
2 1.8V 15 1 + 0.005 50C - 25C 20V 2 45A 0.007 + 20 2 1000pF 2 3 1 1 + 400kHz = 2.2W 5V - 1.8V 1.8V
( )[ (
)(
)] )
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LTC3730
APPLICATIO S I FOR ATIO
The worst-case power dissipation by the synchronous MOSFET under normal operating conditions at elevated ambient temperature and estimated 50C junction temperature rise is: PSYNC 20V - 1.3V = (15A)2 (1.25)(0.007) = 1.84W 20V
A short circuit to ground will result in a folded back current of:
ISC
()
1 150ns 20V + 2 + 3 m 2 0.6H 25mV
( ) = 7.5A

with a typical value of RDS(ON) and d = (0.005/C)(50C) = 0.25. The resulting power dissipated in the bottom MOSFET is: PSYNC = (7.5A)2(1.25)(0.007) 0.5W which is less than one third of the normal, full load conditions. Incidentally, since the load no longer dissipates any power, total system power is decreased by over 90%. Therefore, the system actually cools significantly during a shorted condition! PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 12. Check the following in the PC layout: 1) Are the signal and power ground paths isolated? Keep the SGND at one end of a printed circuit path thus preventing MOSFET currents from traveling under the IC. The IC signal ground pin should be used to hook up all control circuitry on one side of the IC, routing the copper through SGND, under the IC covering the "shadow" of the package, connecting to the PGND pin and then continuing on to the (-) plates of CIN and COUT. The VCC decoupling capacitor should be placed immediately adjacent to the IC between the VCC pin and PGND. A 1F ceramic capacitor of the X7R or X5R type is small enough to fit very close to the IC to minimize the ill effects of the large current pulses drawn to drive the bottom MOSFETs. An additional 4.7F to 10F of ceramic, tantalum or other very low ESR capacitance is recommended in or-
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der to keep the internal IC supply quiet. The power ground returns to the sources of the bottom N-channel MOSFETs, anodes of the Schottky diodes and (-) plates of CIN, which should have as short lead lengths as possible. 2) Does the IC IN+ pin connect to the (+) plates of COUT? A 30pF to 300pF feedforward capacitor between the AMPOUT and EAIN pins should be placed as close as possible to the IC. 3) Are the SENSE- and SENSE+ printed circuit traces for each channel routed together with minimum PC trace spacing? The filter capacitors between SENSE+ and SENSE- for each channel should be as close as possible to the pins of the IC. Connect the SENSE- and SENSE+ pins to the pads of the sense resistor as illustrated in Figure 11.
INDUCTOR LTC3730 SENSE+ SENSE- 1000pF SENSE RESISTOR
3730 F11
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OUTPUT CAPACITOR
Figure 11. Kelvin Sensing RSENSE
4) Do the (+) plates of CIN connect to the drains of the topside MOSFETs as closely as possible? This capacitor provides the pulsed current to the MOSFETs. (The loop area formed by CIN, topside MOSFET and bottom MOSFETs must be minimized.) 5) Keep the switching nodes, SWITCH, BOOST and TG away from sensitive small-signal nodes (SENSE +, SENSE -, IN +, IN -, EAIN). Ideally the SWITCH, BOOST and TG printed circuit traces should be routed away and separated from the IC and the "quiet" side of the IC. Separate the high dV/dt printed circuit traces from sensitive small-signal nodes with ground traces or ground planes. 6) Use a low impedance source such as a logic gate to drive the PLLIN pin and keep the lead as short as possible.
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LTC3730
APPLICATIO S I FOR ATIO
7) Minimize trace impedances of TG, BG and SW nets. TG and SW must be routed in parallel with minimum distance. Figure 12 illustrates all branch currents in a three-phase switching regulator. It becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. High electric and magnetic fields will radiate from these "loops" just as radio stations transmit signals. The output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives rise
SW1
VIN SW2 RIN
+
CIN D2 COUT
BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MININMUM LENGTH SW3
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to the "noise" generated by a switching regulator. The ground terminations of the synchronous MOSFETs and Schottky diodes should return to the bottom plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. A separate isolated path from the bottom plate(s) of the input and output capacitor(s) should be used to tie in the IC power ground pin (PGND). This technique keeps inherent signals generated by high current pulses taking alternate current paths that have finite impedances during the total period of the switching regulator. External OPTI-LOOP compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure.
L1 RSENSE1 D1 L2 RSENSE2 VOUT
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+
RL
L3
RSENSE3 D3
3730 F12
Figure 12
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LTC3730
APPLICATIO S I FOR ATIO
Simplified Visual Explanation of How a 3-Phase Controller Reduces Both Input and Output RMS Ripple Current The effect of multiphase power supply design significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is divided by, and the effective ripple frequency is multiplied up by the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by, and the effective ripple frequency is increased by the number of phases used. Figure 13 graphically illustrates the principle.
SINGLE PHASE SW V
ICIN
ICOUT
TRIPLE PHASE SW1 V SW2 V SW3 V IL1 IL2 IL3
ICIN ICOUT
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Figure 13
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The worst-case input RMS ripple current for a single stage design peaks at twice the value of the output voltage. The worst-case input RMS ripple current for a two stage design results in peaks at 1/4 and 3/4 of the input voltage, and the worst-case input RMS ripple current for a three stage design results in peaks at 1/6, 1/2, and 5/6 of the input voltage. The peaks, however, are at ever decreasing levels with the addition of more phases. A higher effective duty factor results because the duty factors "add" as long as the currents in each stage are balanced. Refer to AN19 for a detailed description of how to calculate RMS current for the single stage switching regulator. Figure 6 illustrates the RMS input current drawn from the input capacitance versus the duty cycle as determined by the ration of input and output voltage. The peak input RMS current level of the single phase system is reduced by 2/3 in a 3-phase solution due to the current splitting between the three stages. The output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the VOUT/L discharge currents term from the stages that has their bottom MOSFETs on subtract current from the (VCC - VOUT)/L charging current resulting from the stage which has its top MOSFET on. The output ripple current for a 3-phase design is:
IP-P = VOUT (1- 3DC ) VIN > 3VOUT ( f)(L)
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The ripple frequency is also increased by three, further reducing the required output capacitance when VCC < 3VOUT as illustrated in Figure 6. The addition of more phases by phase locking additional controllers, always results in no net input or output ripple at VOUT/VIN ratios equal to the number of stages implemented. Designing a system with multiple stages close to the VOUT/VIN ratio will significantly reduce the ripple voltage at the input and outputs and thereby improve efficiency, physical size and heat generation of the overall switching power supply. Refer to Application Note 77 for more information on Polyphase circuits.
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LTC3730
APPLICATIO S I FOR ATIO
Efficiency Calculation
To estimate efficiency, the DC loss terms include the input and output capacitor ESR, each MOSFET RDS(ON), inductor resistance RL, the sense resistance RSENSE and the forward drop of the Schottky rectifier at the operating output current and temperature. Typical values for the design example given previously in this data sheet are: Main MOSFET RDS(ON) = 7m (9m at 90C) Sync MOSFET RDS(ON) = 7m (9m at 90C) CINESR = 20m COUTESR = 3m RL = 2.5m RSENSE = 3m VSCHOTTKY = 0.8V at 15A (0.7V at 90C) VOUT = 1.3V VIN = 12V IMAX = 45A = 0.5%/C N=3 f = 400kHz The main MOSFET is on for the duty factor VOUT/VIN and the synchronous MOSFET is on for the rest of the period or simply (1 - VOUT/VIN). Assuming the ripple current is small, the AC loss in the inductor can be made small if a good quality inductor is chosen. The average current, IOUT is used to simplify the calaculations. The equation below is not exact but should provide a good technique for the comparison of selected components and give a result that is within 10% to 20% of the final application. The temperature of the MOSFET's die temperature may require interative calculations if one is not familiar typical performance.
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A maximum operating junction temperature of 90 to 100C for the MOSFETs is recommended for high reliability applications. Common output path DC loss:
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I PCOMPATH N MAX RL + RSENSE + C OUTESR Loss N
2
(
)
This totals 3.375W + COUTESR loss. Total of all three main MOSFET's DC loss:
V I PMAIN = N OUT MAX 1 + RDS(ON) + CINESR Loss VIN N
2
()
This totals 0.87W + CINESR loss at 90C. Total of all three synchronous MOSFET's DC loss:
V I = N 1 - OUT MAX 1 + RDS(ON) VIN N
2
PSYNC
()
This totals 7.2W at 90C. Total of all three main MOSFET's AC loss: PMAIN 3(VIN )2 45A (2)(1000pF ) (2)(3) 1 1 + (400kHz) = 6.3 W 5V - 1.8V 1.8V
This totals 1W at VIN = 8V, 2.25W at VIN = 12V and 6.25W at VIN = 20V.
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LTC3730
APPLICATIO S I FOR ATIO
(3)Q G VIN VDSSPEC (f) = (6)(15nC ) VIN VDSSPEC
Total of all three synchronous MOSFET's AC gate loss:
(4E5)
This totals 0.08W at VCC = 8V, 0.12W at VCC = 12V and 0.19W at VCC = 20V. The bottom MOSFET does not experience the Miller capacitance dissipation issue that the main switch does because the bottom switch turns on when its drain is close to ground The Schottky rectifier loss assuming 50ns nonoverlap time: 2 * 3(0.7V)(15A)(50ns)(41E5) This totals 1.26W.
TYPICAL APPLICATIO
OPTIONAL FOR SYNCHRONIZATION 1000pF 5V VID1 IN 30k 10k 1 2 3 4 100pF 27pF 5 6 7 8 9 S1
+
VID1 PLLIN PLLFLTR FCB IN+ IN- AMPOUT EAIN SGND SENSE1+ SENSE1- SENSE2+ SENSE2- SENSE3- SENSE3+ RUN/SS ITH VID2
VID0 PGOOD BOOST1 TG1 SW1 BOOST2 TG2 SW2 VCC BG1 PGND BG2 BG3 SW3 TG3 BOOST3 VID4 VID3
LTC3730
10 1000pF 11 12 13 14 15 16 ITH 17
S1- S2+
1000pF S2- S3- 0.01F 1000pF S3+
470pF 5.1k
1.5nF
VID2 IN
18
VOUT: 0.6V TO 1.75V, 45A SWITCHING FREQUENCY: 300kHz CIN: SANYO OS-CON 25SP68M COUT: 270F/2V x6 PANASONIC SP EEUE0D271R
D1 TO D3: B140A DIODES INC L1 TO L3: SUMIDA 1H/20A CEP125 IROMC-H OR 1H/19A PANASONIC PCC-D126H OR TOKO EH125C
Figure 14. CPU Application 0.6V to 1.75V, 45A Power Supply
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The total output power is (1.3V)(45A) = 58.5W and the total input power is approximately 60W so the % loss of each component is as follows: Main switches' AC loss (VIN = 12V) 2.25W 3.75% Main switches' DC loss Synchronous switches AC loss Synchronous switches DC loss Power path loss 0.87W 1.5% 0.19W 0.3% 7.2W 12% 3.375W 5.6% The numbers above represent the values at VCC = 12V. It can be seen from this simple example that two things can be done to improve efficiency: 1) Use two MOSFETs on the synchronous side and 2) use a smaller MOSFET for the main switch with smaller CMILLER to better balance the AC loss with the DC loss. A smaller, less expensive MOSFET can actually perform better in the task of the main switch.
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 0.1F VID3 IN VID4 IN 5V M5 VIN L3 D3 S3+
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5V VID0 IN
PGOOD 47k 5V 1 M1 VIN L1 D1 S1+ 5V VIN M3 L2 D2 S2+ S2- 0.003 10F 35V x4 S1- 0.003 10F 6.3V x3
0.1F
VOUT
M2 0.1F
+
COUT
+
1F
10F
M4
VIN CIN 5V TO 24V 68F 25V
0.003
M6
S3-
M1, M3, M5: IRF7811W OR FDS6688 OR Si7860DP OR HAT2168H M2, M4, M6: Si7856DP OR HAT2165H
LTC3730
PACKAGE DESCRIPTIO
7.8 - 8.2
0.42 0.03 RECOMMENDED SOLDER PAD LAYOUT 5.00 - 5.60** (.197 - .221)
0.09 - 0.25 (.0035 - .010)
0.55 - 0.95 (.022 - .037)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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G Package 36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
12.50 - 13.10* (.492 - .516) 1.25 0.12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 5.3 - 5.7 7.40 - 8.20 (.291 - .323) 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2.0 (.079) 0 - 8 0.65 (.0256) BSC 0.22 - 0.38 (.009 - .015) 0.05 (.002)
G36 SSOP 0802
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